Office: EBU3B 3212
Office Hours: Wed 12-1; Thurs 3-4; By appointment
Teaching AssistantsSriskanda Shamasunder
Office Hours: Wed 1pm-3pm
Office Hours: Mon 4.30-6.30
Course discussion board: Piazza. Required reading. Get signed up.
This course will describe the basics of modern processor operation. Topics include computer system performance, power issues, memory, multiprocessors, pipelining, instruction-level parallelism, storage systems, GPUs, and virtual machines.
|Midterm||25%||The midterm is on 6th May, 2014.|
|Final||25%||The final will be cummulative.|
Additional notes about grades in this course:
Calculating grades I compute grades using an Excel spread sheet. In the interests of transparancy, the current grade sheet (with identifying information removed) is avaiable in PDF format. The grade sheet contains all the information about curves and how the grades are computed. It is somewhat sophisticated, if you find bugs please bring them to my attention. Please note that some versions of OpenOffice do not perform the calculations properly, and will give incorrect results.
The grading systems is based on a 13 point (F through A+) scale. For each assignment/test/etc, the sheet computes the letter grade (rounding up, when needed) according to a curve for each assignment (specified at the bottom of each assignments column). Your final grade is the weighted average of these grades.
We do our best to record grades accurately, but you should double-check.
Errors in grading If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem.
For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.
Final grades If you have a problem with your
I will post the slides for most lectures.
Reading should be done before class on the day they are listed. It is essential that you do the readings.
|Tuesday, April 1||Introduction and Administrivia||00_Introduction_plus_logistics.pdf|
|Thursday, April 3||Silicon Scaling||
(this is the original paper about Moore's Law): Cramming More Components Onto Integrated Circuits, , Proceedings of the IEEE 86(1):82-85, Jan 1998 link.
|Tuesday, April 8||Measuring and Thinking About Performance; Power||
Conservation cores: reducing the energy of mature computations, , Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems, New York, NY, USA, 2010, pages 205-218
|Thursday, April 10||More on power||02_Amdahls_Law.pdf|
|Tuesday, April 15||Instruction Sets||
The case for the reduced instruction set computer, , SIGARCH Comput. Archit. News 8(6):25-33, 1980.
CryptoManiac: a fast flexible architecture for secure communication, , ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture, New York, NY, USA, 2001, pages 110-119 link.
|Thursday, April 17||Memory Hierarchy||
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, , SIGARCH Comput. Archit. News 18(3a):364-373, 1990.
Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Norman P. Jouppi, ISCA '98: 25 years of the international symposia on Computer architecture (selected papers), New York, NY, USA, 1998, pages 71-73.
|Tuesday, April 22||Processor Pipelines and Out-of-Order Execution||
Chapters 3.1, 3.4-3.6, 3.8
An efficient algorithm for exploiting multiple arithmetic units, , IBM J. Res. Dev. 11(1):25-33, 1967.
|Thursday, April 24||No class||TBA|
|Tuesday, April 29||Processor Pipelines and Out-of-Order Execution||
|Thursday, May 1|
|Tuesday, May 6|
|Thursday, May 8||Chip Multiprocessors||
SLOCA: Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency 1.1 -1.4
|Tuesday, May 13||Chip Multiprocessors|
|Thursday, May 15||Multiprocessor memories||
SLOCA: A Primer on Memory Consistency and Cache Coherence. Chapter 1-3.7; 5.1-5.2.2
|Tuesday, May 20||Multithreading||
|Thursday, May 22||Branch Prediction||
Combining Branch Predictors, ,Tech. Rep. TN-36m, Digital Western Research Laboratory ,June 1993
|Tuesday, May 27||Storage||
|Thursday, May 29||Storage + potpourri||20_Storage_2.pdf|
|Tuesday, June 3||GPU||18_GPUs.pdf||Project 1;|
|Thursday, June 5|
|Thursday, June 12|