# CSE 140 Syllabus

## Textbooks

Following are the suggested texts for this course :

• [Harris]: Digital Design and Computer Architecture by David Mooney Harris and Sarah L. Harris
• [Lang]: Digital Systems and Hardware/Firmware Algorithms by Milos D. Ercegovac and Tomas Lang

## Peer Instruction : Clickers

The course lectures will follow a Peer Instruction format, a teaching model which places stronger emphasis on classroom discussion and student interaction. As part of this, you will be assigned an iClicker, which you will need to register. You will be expected to have completed the assigned reading and ready to discuss with your classmates. The iClicker can be purchased at the UCSD book store.

Your final grade for the course will be based on the following weights:

• 7% Homework
• 30% Midterm 1
• 30% Midterm 2
• 30% Midterm 3
• 2% Final Exam (Optional Bonus, Take home)
• 3% Class Participation

To pass (C or better) you need to get at least 40% overall.

## Schedule

Tue 04/01 1 Course Overview - The digital abstraction and basic logic gates
[Harris] Chapter 1
Thu 04/03 2 Combinational Logic: Truth tables, Boolean Algebra, Axioms - DeMorgan's, Consensus, Covering, Shannon expansion, Boolean Equations (sum of products, product of sums), reduction of boolean expressions using boolean algebra
[Harris] Chapter 2, Section 2.1-2.4
Fri 04/04 HW 1 posted
Tue 04/08 3 Combinational Circuits: Hardware reduction, bubble pushing, 2 variable K-maps
[Harris] Chapter 2, Section 2.5, 2.7
Thu 04/10 4 Optimizing Combinational Circuits: Logic minimization with multivariable K-maps, Handling don't cares, prime and essential prime implicants and implicates
[Harris] Chapter 2, Section 2.7
Fri 04/18 HW 1 due , HW 2 posted
Tue 04/15 5 K-Maps in higher dimensions, K-map to product of sum minimization
Thu 04/17 6 Universal Gates, Universal sets with NAND, NOR and XOR gates, block diagram transfers
TBD
Fri 04/18 HW 2 due
Tue 04/22 Midterm 1
Thu 04/24 7 Sequential Network Components: Bistable memory elements, latches, flip flops (SR, D, T, JK) and registers
[Harris] Chapter 3, Section 3.1, 3.2
Fri 04/25 HW 3 posted
Tue 04/29 8 Sequential Network Specification: Finite State Machines
[Harris] Chapter 3, Section 3.3, 3.4.1, 3.4.2
Thu 05/01 9 Sequential Network Implementation: Moore and Mealy Machines
[Harris] Chapter 3, Section 3.4
Tue 05/13 Midterm 2
Th 05/15, Tu 05/19 10 Sequential Network Timing Analysis
[Harris] Chapter 3, Section 3.5
Tue 05/20 Thu 05/22 11 Standard Combinational Modules: Decoders and Encoders, Multiplexer, Demultiplxer
[Harris] Chapter 2 Section 2.8.2, other?
Tue 05/27 12 System Design I
[Lang] Chapter 9 , Section 9.2
Thu 05/29 13 System Design II
[Lang] Chapter 9 , Section 9.2
Fri 05/30 HW 5 due
Tue 06/3 17 Final review
Thu 06/5 Midterm 3
Thu 06/12 Final Exam (take home)

Last updated: Fri Feb 14 16:15:24 -0800 2014 [validate xhtml]