cse.240b Parallel Computer Architecture - Spring 2013      |
Course GoalsThis class is designed to enable students to follow the latest developments in computer architecture, especially those related to parallel computer architecture. Although this is clearly useful for those who wish to do research in computer architecture, it is also useful for those who work in related areas or who have general interests. The class strives for these goals through four aspects:
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Directory Coherence | Memory Consistency |
Interconnection Networks | Synchronization |
Transactions | Streams |
Vector Architectures | Heterogeneous Multi-core |
Simultaneous Multi-threading | Cell Architecture |
GPUs | Tiled Architectures |
CUDA | Cilk |
Arsenal Style Processors | Dark Silicon |
Your Topic Here |
April 2 | The course forum is up! Make sure to sign up in order to receive important course details. Click here to join. You must give your name as your nickname, and enter in your UCSD email address in the information box. It may take a day or two for you to be comfirmed. |
April 2 | Yes, one analysis per paper! No analysis for textbook items UNLESS specified below. |
Final Grade | = | Proof of Reading | * |
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Day | Due |
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Epoch I | Previous Friday, 11 p.m. |
Epoch II | Tuesday, 4:30 p.m. |
Day | Due |
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Tuesday Classes | Previous Wednesday, 11 p.m. |
Tue, April 02 | Overview, Administrivia | ||
(Epoch 2) Tue, April 02 | |||
Tue, April 09 | Tech Trends | Asanovic et al, "The landscape of parallel computing research: a view from berkeley", Tech Report UCB/EECS2006-183. | |
(Epoch 2) Tue, April 09 | Case Study: Raw, a Simple Parallel Machine | The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs, Taylor et al, IEEE Micro March/April 2002. The Raw Specification, v 5.0, The Raw Specification, v 5.0. | |
Tue, April 16 | Cache Coherence I | Read "A Primer on Memory Consistency and Cache Coherence", Chap 1-4. | |
(Epoch 2) Tue, April 16 | () | ||
Tue, April 23 | Cache Coherence, Part II | Read "A Primer on Memory Consistency and Cache Coherence", Chapter 6-8. | |
(Epoch 2) Tue, April 23 | () | ||
Tue, April 30 | Data Parallel | H & P Chapter 4 (Data-Level Parallelism in Vector, SIMD and GPU). | |
(Epoch 2) Tue, April 30 | GPUs/CUDA & Tera | NVIDIA Tesla: A Unified Graphics and Computing Architecture Lindholm, et al. Micro, IEEE Mar 2008. Scalable Parallel Programming with CUDA. Nickolls et al. ACM Queue. 2008. | |
Tue, May 07 | Data Center | Read H&P Chapter 6. | |
(Epoch 2) Tue, May 07 | () | Read Synthesis Lecture: "The Datacenter as a Computer" | |
Tue, May 14 | Dark Silicon | The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future, IEEE Micro 2011, Goulding-Hotta. Read 50 percent of Synthesis Lecture on Dark Silicon. | |
(Epoch 2) Tue, May 14 | Read Rest of Synthesis Lecture on Dark Silicon (preprint). Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, MICRO 2003, Tullsen ISCA 2010; Horowitz; Understanding Sources of Inefficiency in General-Purpose Chips | ||
Tue, May 21 | Parallelizing Compilers | Read Synthesis Lecture on "Automatic Parallelization: An Overview of Fundamental Compiler Techniques", Chapter 1-7. | |
(Epoch 2) Tue, May 21 | () | ||
Tue, May 28 | On-Chip Networks | Synthesis Lectures on On-Chip Networks | |
(Epoch 2) Tue, May 28 | () | ||
Tue, June 04 | Last Test | ||
(Epoch 2) Tue, June 04 | slides |