cse141L: Introduction to Computer Architecture Lab

Center Hall 113
Monday, 3:00-3:50pm
Winter, 2013
Shortcuts: Schedule Labs


Steven Swanson
Email: swanson @ cs.ucsd.edu
IM (not email): professorswanson@{AIM, Yahoo!, google talk, MS Messenger}
Office: EBU3B 3212
Office Hours: Monday 10-11; Thursday 11-12 (and by appointment)
UCSD homepage

Teaching Assistants

Mark Gahagan
Email: mgahagan @ cs.ucsd.edu
Office: EBU3b B250
Office Hours: Tuesday 2:30pm-3:30pm, Thursday 5:00pm-6:00pm

Raymond Paseman
Email: rpaseman @ cs.ucsd.edu
Office: EBU3b B270
Office Hours: Wednesday 6:00pm-8:00pm

Thinh Nguyen
Email: thn024 @ ucsd.edu
Office: EBU3b B250
Office Hours: Sunday 10:00am-2:00pm, Monday 4:00pm-7:00pm, Tuesday 4:00pm-7:00pm,

Course discussion board: cse141L Discuss . Required reading. Get signed up. You should also be subscribed to the Announcements Google Group for the course. Mandatory to sign up for both the groups. All course announcements will be posted by TA/Prof in "Announce" group only. If you have any personal queries, you can post to staff group by sending an email to: cse-141L-sp13-staff@eng.ucsd.edu

Course Description

This is the laboratory class associated with cse141: Introduction to Computer Architecture. Over the course of the quarter, you will design a processor that implements a large subset of the MIPS instruction set architecture. It will provide you the chance to grapple first-hand with the issues of processor design.

Text books

Required: Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, Patterson & Hennessy, Morgan Kaufmann, 4th Edition (Revised) This is the text for 141 and 141L. The text is mandatory.


There are two ways to get an "A" in this class. One is to implement a working pipelined MIPS processor by the end of the quarter that executes simple programs compiled using the GCC cross compiler. This is the grading option you should strive for. You can get an "A+" by adding some interesting and exciting feature to your processor during the final lab.

Doing well (i.e., getting an "A" or "A+") in the course will also demonstrate your ability to build a large, complex computer system, and it gives me a concrete and compelling reason to recommend you for jobs (or graduate school positions) that require those kinds of skills.

The other way to get a good grade is to do well on the labs. If your processor doesn't turn out as well, I will consider your performance on the labs and participation (see below). Your grade will be at least the maximum of the "your processor works" grade and the lab assignment grade.

In addition to the labs, you should be an active contributer to the web board. The tools are challenging and sometimes buggy. Your classmates (in addition to the course's staff) are an excellent resource for help with the tools.

This class is about doing. You will learn almost everything you learn in this class by doing it. This means that you (or your team) must do all your own work. As long as you meet this criteria, you can consult with and discuss your project with other groups. We have structured the course (by not having a curve) so that there is no incentive to be stingy with your knowledge of the tools or in sharing your expertise with your classmates.

Late lab write ups If you cannot complete your lab on time, you can turn it in late, but your grade will be penalized. The penalty is one letter grade per 24 hours extension. Up to 2 extensions are possible. For example, if the labs are due at 5pm, you have until 5pm the next day to turn it in with one letter grade penalty, and until 5pm the day after to turn it in with a two letter grade penalty, and so on.

Keep in mind that even if your lab write up is late, you are still responsible for completing the lab, since the labs build on one another.

Labs 100% There are six labs of equal weight.

Additional notes about grades in this course:


Items in the schedule more that one week in the future are subject to change. Check back for updates for the assigned readings, etc. The date for the midterm will not change, however. Nor will deadlines for homeworks/projecsts that have been assigned be move earlier.

I will post the slides for most lectures. Since the slides contain material I am not allowed to distribute publically, they are only available from on campus or via the campus proxy. Instructions for setting up the proxy can be found here. Using the proxy is useful in general, since it gives you full access to the libraries and other resources from off campus.

Date Topic Readings Slides Due Notes
Monday, April 01 Administrivia; Overview of the course; Lab 1 assigned; Verilog I 00_Introduction.key.pdf Tips for using Altera Tools
Monday, April 08 Verilog II; datapath and control design. Lab 2 preview. Lab 1 due 02-Verilog2.pdf,
Lab 1 is due at 3PM on the Monday the 8th
Monday, April 15 Verilog II; datapath and control design. Lab 3 preview. Lab 2 due 04_ControlAndLab3-sp13.pdf Project 2;
Monday, April 22 Verilog II; datapath and control design; Lab 4: Branches preview. Lab 3 due 05_Lab4.pdf Project 3;
Monday, April 29 Lab 4 questions
Monday, May 06 Lab 5: 5 Stage preview, Lab4 Due 06_Lab5.pdf Project 4;
Monday, May 13 Lab 5 questions
Monday, May 20 Lab 6 Preview
Monday, May 27 Memorial Day
Tuesday, May 28 Lab 5 Due Project 5;
Monday, June 03 Lab questions
Monday, June 10 Lab 6 Due

Integrity Policy


Lab 1: Be a Hardware Hacker!
Lab 2: Single-Cycle MIPS Datapath
Lab 3: Single-Cycle MIPS Control
Lab 4: Single-Cycle MIPS Branches
Lab 5: 5-Stage MIPS Processor
Lab 6: Bells and Whistles