cse141L Lab 1: Be a Hardware Hacker!


Part 1: Log into the discussion board

Due: April 8

There is a link to the coures discussion board on the course homepage. Your login is your official UCSD user name (i.e., your @ucsd.edu email address without the "@ucsd.edu" part). Password is your PID.

Take some time to explore the discussion boards features. If you like, you can configure it to send everything to you by email, so you don't have to visit the website regularly.

Reading the web board is mandatory. It is the only place that all announcement related to class will be posted.

Need an account? If you are enrolled through concurrent enrollment or, for some other reason do not have an account, email Hung-Wei with your prefered username and he will create an account for you.

Deliverable

  • Post a reply under the "Welcome" message in the administrative forum. You don't neet to hand anything in. If you are enrolled in 141 as well, you only need to post once.
  • Due: April 8

    Part 2:

    Due: April 8

    Lab 1 is a preparation stage for future labs, and consists of two parts - Xilinx ISE and Verilog. In Lab 1, you will install Xilinx ISE and follow a step-by-step tutorial to learn essential concepts and working flow in hardware designs. For those who used Xilinx ISE in 140L, this lab sould be very easy. Otherwise, you should START NOW - there might be many unexpected problems. If you have any question regarding this lab, please post it on the webboard.

    Tools:

  • Get Xilinx WebPack 10.1 from this link. You will be using this software all quarter. Note: you will be using version 10.1, but many of the screenshots in this lab and other labs may be of a slightly older version--so what you see may be a little different than what is pictured here.
  • Xilinx Quick Tutorial

    Xilinx provides a good step-by-step tutorial. With this tutorial, you will be able to learn how to perform various activities in the hardware design process. It should take less than two hours to follow the tutorial.

    A Simple 8 bit Adder

    Now that you know how to use XilinX ISE, we will examine a few aspects of hardware design. For more information, I highly recommend you skim through chapter 2 and chapter 5 of Xilinx In-depth Tutorial.

    32 bit Adder

    Multiplier

    Free Form Experiment

    Useful Resources

    Deliverable

    • No lab interview for lab 1. In future labs, you will have interview sessions with a TA to show your results.
    • Submit your report for the questions above to the TA via e-mail by the due date before the beginning of the class.
      • Answer all of the questions (10) found in the lab description.
      • The report should be in a single PDF file (including answers to questions, verilog source code, graphs, screenshots, etc). There are many tools out there capable of integrating text and graphics and producing PDF files (OpenOffice does a pretty good job).
      • Name your PDF file cse141L-lab1-LastName-FirstName.pdf with your last name and first name substituted for LastName and FirstName, respectively.
      • The subject line of your email should read "[CSE141L] Lab 1 Submission - LastName, FirstName".

    Due: April 8