CSE 140L Lab 2, Part 0 - Sequential Logic Lab Tutorial
Spring 2009, Professor Cheng, TAs Thomas Weng, Renshen Wang, Chengmo Yang, Mingjing Chen
This tutorial will demonstrate how to construct an asynchronous 2-bit
counter using Quartus II. By following this tutorial, you should be able to
implement this circuit in the board, such that it will count every second, use
push button 2 to clear (reset), and display D1 and D0 on LED digit 1 and digit 2
respectively. The steps could be as follows:
2. Next we create the clock source. The board provides us a 50-MHz
oscillator which can be used as a global clock input. However, we need some
module to convert it to the 1-Hz clock. We provide the VHDL code
clk_div.vhd to serve this purpose. It can convert the
50-MHz clock to various other frequencies, from 1-MHz to 1-Hz. Now copy this
file to your working directory and then create a hiearchical block called
clk_div. Double click the block, then it will automatically connect to the VHDL
4. Copy the file Binary_display.bdf to your working directory. Construct two hierarchical blocks for display and connect them to the outputs of two flip-flops respectively. You must be familiar with that already. However, instead of connecting 7 output pins to the hierarchical block directly, we connect one bus output to each block and name them as LSD[6..0] and MSD[6..0] respectively. Specify the mapping properties for each LSD to LSD, MSD to MSD respectively, as shown in the following screen shot.
5. In other place of the diagram, create 8 output pins for each block. Each pin is connected to a wire, which is name as LSD, LSD, ... The Quartus II compiler will automatically connect them to the buses. Thus, it is important to keep the name consistency between buses and output wires.
6. Specify pin numbers in the pin locator for each input and output. The 50Mhz clock is available as an input, which is PIN_L1 for DE1 board.
7. Now compile the
design and download it to the board. You should be able to see the LED counts
9. Create an input wave form file and add 2 input pins clk and PB2 to it. Right click the clock pin, choose Value-Clock.. in the menu and specify the clock period as 20 ns or 50 MHz, as shown below. Also, right click the PB2 pin, choose Value-Forcing High (1), since we do not want to clear the counter.
10. Perform the
functional and timing simulation as Lab 1. You will obtain the following
Timing Simulation Results: