CSE 141L: Computer Architecture Lab


Lecture Slides | Labs | WebBoard | Schedule | Basic Course Information


Announcements:


Course Overview:

Welcome aboard the AwesomeCore Inc. team. As part of your term-long project, you will be working creating a custom microprocessor. We will give you the specifications for this new processor but you will be in charge of creating a custom ISA for it and seeing its design through synthesis onto an FPGA. Your job won't be easy. In order to keep up with the big boys at Advanced Nano Devices and Letni Inc., you are going to have to use all of your computer architecture knowledge to create a pipelined processor that has best-in-class performance. Luckily you will have access to the powerful Xilinx ISE design kit and a partner of your choosing.

We know you have the experience and dedication necessary to succeed and can't wait for you to help AwesomeCore become the market leader in microprocessor design. If you have any questions, please contact your project managers, Michael and Sat.

AMD Quad-core Phenom Processor


Lecture Slides

Date Topic
May 13 Week 7 Update (Lab 4, Part 2 Overview)
May 6 Week 6 Update (Lab 4, Part 1 Overview)
April 29 Week 5 Update (Lab 3, Part 2 Overview)
April 22 Week 4 Update (Lab 2 Review, Lab 3 overview)
April 15 Week 3 Update (Lab 2 Status)
April 8 Verilog Tutorial, Part Deux
April 1 A Brief Intro to Verilog


Labs

Lab Title Due Date
5 Processor Optimization June 3
4, Part 2 Execution Unit Control and Test May 20/27
4, Part 1 Execution Unit Datapath May 13
3, Part 2 Creating an Assembler May 6
3, Part 1 Designing an ISA - How to Talk to Your CPU May 2
2, Part 2 Processor Front-End - Fetch Control and Testing April 22
2, Part 1 Processor Front-End - Fetch Datapath April 15
1 Tools of the Trade April 8


Basic Course Information


Evaluation

Your progress for this project will be measured in two ways: For the demonstration, you will meet with Sat to explain your progress and to provide a live demonstration of the current status of your project. He will expect you to be able to intelligently discuss your design choices. You will also be required to provide progress reports as a written supplement to the demonstration. We will provide specific questions that you should briefly answer in your progress report.

Ultimately, your grade for this course will be based on your ability to complete all parts of the project satisfactorily. There will be hard deadlines for each part of the progress, with no late submissions accepted. If, at the end of the project, you have met all the deadlines ahd have a processor meeting all the specifications, you should expect to receive a good grade.

Class Participation

At AwesomeCore Inc. we value our team-based atmosphere. Your active participation in class will help contribute to a vibrant lab atmosphere that will help everyone become more productive hardware engineers. As such, approximately 15% of your grade will be based on participation.

You can get credit for participation either by actively engaging in the lectures or, possibly more important, contributing to AwesomeCore's state-of-the-art online help forum: WebBoard. Your project managers, Sat and Michael, will answer all policy questions on the WebBoard but time constraints limit them from immediately answering all project related questions. As such, you will have the opportunity to garner the respect of your colleagues and managers by answering their questions on the WebBoard. Sat and Michael will eventually answer any unanswered questions (with the possible exclusion of difficult, existential questions) but for the betterment of the class (and your grade) you should answer questions too.

Regrade Policy

If you would like to challenge the grade you received for any portion of the project, you must abide by the following guidelines:
  1. You must submit a request in writing describing the issue with the grade.
  2. We reserve the right to regrade the entire assignment, so your grade can go up or down.
  3. You must submit a regrade request within 1 week of the day the assignments are returned.