CSE 140L Spring 2008: Announcements | Syllabus | Schedule | Materials
CSE 140L: Digital Systems Lab
Spring 2008
Step by step example
(schematic flow)
Since the software we will use is preinstalled in all PCs
of our Lab, so you don’t need to worry about installation.
If you need to install the ISE webpack
on your own PC, go here.
The in-depth tutorial can be found here.
You are recommended to read it through as we proceed, but for now, you can
follow the simple example to have a feel about it.
If you have problem of seeing pictures in this example,
please try firefox web browser, which can be freely
downloaded. You can type “firefox download”
in google to get the download link.
1.
Starting the ISE software
Double click the ISE Project Navigator icon (
) on
your desktop or select Start->All
Programs->Xilinx ISE 9.2i ->Project Navigator.
You should see the following window:
Click OK button and the Tip window will close.
2. Creating a New Project
From Project Navigator, select File->New Project. The New Project
Wizard appears.
Type the project name you want in
the Project Name field.
Type the path you want to install
the project in the Project Location field.
Verify that Schmatic
is selected as the Top-Level Source Type and clock Next.
The New Project Wizard –
Device Properties windows appears.
Select each field in the Device
Properties window as indicated in the above figure. Make sure to confirm to
enable enhanced design summary, and then click Next.
Select New Source, then next window will be:
Click Schematic from the left
hand side list, and then type the name of the schematic in the File name field.
Then click Next.
Then the source file name and type will appear.
Click Next.
A summary window containing
project information shows up. Click Finish.
Then you will be asked whether
any existing sources need to be imported, just click Next. Then another summary
window appears and just click Finish.
You will see:
There are Sources window and
Processes window at left side and design summary at right side. Click on the example.sh tab at the bottom to see the schematic
Make sure the Symbol tab is
selected at the top-left Sources window.
In the Categories listbox, scroll down to select
Logic, and in the Symbols group, select and2, then move your cursor to the main
schematic window on the right and you will see a schematic symbol attached to
your cursor. Left-click to place the symbol on the schematic.
Press ESC to detach the symbol from the cursor, and then press F8 to zoom in
the schematic window. Then you will see:
Next, we need to define I/O of
the logic gate. Press Ctrl-G or click on the Add I/O Marker tool in the toolbar to start placing I/O markers,
which are connected to outside. Place I/O marker directly
over the connection point for the two inputs and one output of the and2 gate.
The result should be:
“XLXN_*” are names
arbitrarily defined by the tool, we need to rename them. Click on
“XLXN_1”, and you will see it becomes red.
Then right click, a menu appears,
and choose
Type “A” to replace
“XLXN_1”, then click OK.
Then repeat the same steps for the other two ports, we want to rename
XLXN_2(the other input of the and2 gate) B, and rename the output A_and_B.
The results are as follows:
Then save the example.sch
file.
2. Generating test bench waveform
Click the Sources tab under the
Sources window at top-left. Choose example.sch and
right-click, and select Add New Source.
Select Test Bench Waveform, and then type the file name as “example_wave”, and then click Next.
Click Next and Finish in the
following two windows.
Then you will see:
We need to specify Combinatorial in Clock Information
field, since our simple circuit does not have clock.
Leave other parameters unchanged
and click Finish.
Then we come back to the main
window and see:
The above figure is shown under
the tab of example_wave.tbw, which is the test bench
waveform we just created.
Here we can see the two inputs A
and B and output A_and_B, all of which has zero
values from time 0 to time 1000ns.
Move your cursor to the row and
input A, click the flat waveform somewhere, you can see the waveform changes
from 0 to 1. By this way, we can define our input waveforms.
Now we need to specify A so that:
0 to 1 transition happens at 200ns, and 1 to 0 transition happens at 600ns.
For B, we need the 0 to 1
transition happens at 400ns, and 1 to 0 transition happens at 800ns.
The resulted waveform looks like:
Save your test bench waveform.
In the Sources window, change the
“sources for” from Synthesis/Implementation to Behavioral Simulation.
Choose the tbw
file just appears, and then expand the Xilinx ISE Simulator
in the lower processes window, and double-click Simulation Behavioral Model.
You can see the tool running for a
little while and then the following window shows up:
From the simulation result, we
can verify the correctness of our design, and check the timing information.
4. Assigning ports to pins
For the ports defined in
schematic to control components on the board, they must be connected to pins on
FPGA. This process is called pin assignment.
To do this, first we need to
switch back from behavioral simulation back to synthesis/implementation, click on the example.sch
in the Source window, expand the User Constraints
in the Process window, and double click on the Assign Package Pins. Then a
window prompts up asking you to add a UCF(User Constraint File) into your
project, click yes.
Xilinx PACE will open up, the window looks like:
The left side shows the ports in
the design, and the right side shows FPGA, click Package View tag at the bottom and the diagram of unconnected pins
of the FPGA are shown.
Connect pins to the ports by
clicking in the Loc box of each port, and typing in the proper pin, as follows:
Here AH1 and AH2 are pin
locations for user push buttons, and AC4 are for user LED0. For a complete UCF
file list, click here. If these
file, you can find pin locations for all input/output ports provided by FPGA.
Where you are entering the
location, you should see the corresponding pin location fill in with blue on
the right side pin diagram. Leave other field unchanged for now. Click Save, and then a window prompts up to
let you choose bus delimiter, choose “XST Default”, and then click OK.
Close PACE.
4. Generating a programming file
Click “example.sch”
source file, and then double click Generate
Programming File from the lower process window. This will run all of the processes necessary to create a
file that can be downloaded onto the board to program the FPGA.
This process may need a few
minutes, which is indicated by 
icon and
the output information from console.
The process complete when the 
appears
and “Process "Generate Programming File" completed
successfully” is shown in console.
If you see
, it
means errors occur, and all errors must be resolved before programming file can
be generated. You can check the errors more easily by click on the Error tab.
If you see 
, it
means warning occur, which can be examined under Warning tab.
Please
note:
--Warnings
are usually something unexpected by the software, and probably leads to error.
It is strongly recommend that you check warnings and resolve them before
generating programming file.
--If you
receive a warning "WARNING:ProjectMgmt - ...
line 0 duplicate design unit: 'Module|switch'",
it can safely be ignored. If after resolving warnings, a successfully run
process still shows a next
to it, just leave it. It is a bug in ISE.
4. Programming the FPGA with iMPACT
The board should already be
connected with power cable, as shown below. If not, you can connect it. Also
check the USB cable connection.
Find the switches SW9 and SW8,
which are close to the RESET push button and PS/2 port, and make sure these
switches are all turned off/low.
Turn on the power switch, located
next to the power cable connection, and the green JTAG LED D20 should turn on.
You will also see the red blinking LED D11, close to the DIMM slot and CF card
port. It indicates there is no CF card connection and can be ignored for now.
If the board has not been connected
to the USB
In ISE Project Navigator, expand the Generate Programming File in Process
window and double-click the Configure
Device (iMPACT):
After that, the iMPACT
window should appear:
Make sure the “Configure devises using
Boundary-Scan(JTAG)” is selected and then click Finish.
If iMPACT
successfully find the board, 3 devices will appear in the right window, and a
dialog box will appear:
If iMPACT fails to
find the board, you will see:
Click OK, and try again to get Windows to
recognize the board by unplugging the USB cable, plugging it back and then
holding down the RESET button for about 3 seconds. Click on the Initialize Chain(
) button
to scan your board again.
In the three devices, the last one
“xc2vp30” is the FPGA we need to program, but iMPACT
will ask you to program from the first, indicated with filling green with the
first device. Simply click Bypass.
Do the same for the second device.
When iMPACT is asking
to program the last device, choose “example.bit”
file then click Open.
Then click OK
again:
If you see the following warning window
regarding to clock change, you can ignore it by clicking OK.
Sometimes, iMPACT may
not prompt you to assign configuration files to the three devices. If it does
not, you can do it yourself by right-clicking on the FPGA (xc2vp30) and
choosing Assign New Configuration File.
In the main window, right click the xc2vp30
FPGA and select Program.
Then the following window appears. Leave all
boxes unchecked and then click OK.
i
After the command is executed, there will be a
blue box with “Program Succeeded” in it.
The red "Done" LED on the board (D4)
should light up, indicating that the FPGA has been programmed.
Now, if you push RIGHT button or LEFT button,
LED 0 should turn on, otherwise, it turns off.
Remember that LED turns on when it has value of
zero, and push button sends zero when being pushed down, our and2 gate works
correctly!
Congratulations! You have just done
your first circuit in schematic flow!