Lab 3b: Materialize Your Processor - Control
CSE 141L, Spring 2007, Donghwan Jeon
Due 5/29(Tu)
You should work on this lab with your team from lab 2.
Overview
Finally, it is time to make your processor work. In lab 3b, you will implement the control logic of the processor on top of the datapath implementation you made in lab 3a, and verify it with behavioral and post-route simulations. First, you will write your own testbench which tests all the instructions your ISA support. Then your processor will run our official benchmark - SuperGarbage. You will be provided an automated test environment to easily load applications into your processor and evaluate their performances.
Deliverables
- Submit relevant source files (zipped) via e-mail to TA (djeon AT cs) by 10:00am, Tuesday 5/29. Your email title should be "[CSE141L] lab 3b, name0, name1".
- Leave your hardcopy report in TA's mailbox. The mailbox is located on the second floor of EBU3b by 5:00pm, Tuesday 5/29.
- All Verilog designs must be synthesizable and implementable.
- For Verilog implementations, use consistent and readable naming style. The naming convention, proper indentation, and style will be graded.
Control Logic
Q1. Complete your design by implementing control logic. Keep your verilog as clean as possible. Naming convention, proper indentation, and style will be graded. Include all the source files in your hardcopy report.
Instruction Test
The first test your processor has to pass is a simple instruction test. Write a simple assembly program which uses all the instructions in your ISA except in and out. in and out will be tested in SuperGarbage benchmark with a provided testing environment. Generate a COE file either manually or with your assembler, and verify that your processor successfully handles all the instructions in a behavioral simulation. Try to make your test program as concise as possible while it covers all the instructions.
Q2. Include your test assembly file in the hardcopy report, and explain your testing strategy. Make sure that it covers all the instructions in your ISA. Also include the behavioral simulation result in the report, and explain the simulation result.
The remainder of the lab will be posted soon!
In the remainder of the lab, you will use a provided test infrastructure to run SuperGarbage applications with your SuperGarbage VM. In addition, you will be able to evaluate the performance of your processor.