CSE 141L
Project in Computer Architecture

Spring 2005

Instructor: Pramod V. Argade (p2argade@cs.ucsd.edu)
Office Hours: Wednesday: 5 PM - 6 PM (will be held in AP&M 2444)

Announcements (6/04):

• New Lower Static counts uploaded (June 4th, 2005)
• Here is a tutorial for logic works RAM and ROM components.
• Turn in your final assignment Lab 4 circuit via email to all the TAs by 6:30 pm Tuesday, May 31st.
• Turn in your printed report to Anjum by 6:30 pm in the lab 2444 by 6:30 pm Tuesday, May 31st.
• You must make an appointment with a TA to demo your lab 4 in the 10th week (May 30th - June 4th).
• Dynamic instruction counts that are working in lab 2, for a given group are.

  Best (Sean Nyberg)	Worst
  Mean - 67	Mean - 764
  Median - 269	Median - 1102
  Mode - 131	Mode - 1981

   

• Static instruction counts that are working in lab 2, for a given group are. If your static counts for a running program are better than this, please contact Anjum.

  Best (Eric Saunders, Richard Lee, Dave Eltgroth | Jimmy Phan , Vinh Huynh)	Worst
  Mean - 23 | 26	Mean - 113
  Median - 29 | 33	Median - 92
  Mode - 74 | 56 | 49 (Worley & Alvarez)	Mode - 202

• Test cases for lab 2.
• mean = 254
• mean = 16
• median = 5, sequence in increasing order
• median = 5, sequence in decreasing order
• mod = 1
• mod = 2 or 7
• You must make an appointment with your TA to demo your LAB 3 (Datapath) within before Thursday (5/19). EMAIL the TAs for the available time slots left.
• EMAIL Lab 3 to Anjum and Huayong (Kevin) by attaching it as a zip file containing your logic works file.

• You will sign up for time slot to demo your program to one of the TAs in this week. The sign up sheet will be passed out in the lab lecture.

• You DO NOT need to turn in the timing diagram for this lab, if your circuit has all the displays that are needed to show the result and input of all operations.

• Xilinx Policy: (updated - May 15th) You CAN use Xilinx for Lab 3 and Lab 4 As long as you can create a RAM component that can read in a .dmi text file for the final Lab 4 Demo. Please talk to one of the TAs or Prof. for the details.
• An excellent tutorial on LogicWorks written by past TAs. The directions to print the timing waveforms are in the first part of the tutoria. To print the circuit, you simply choose "print" command from the file menu in your opened circuit.
• LogicWorks 4 Tutorial
• LogicWorks 4 Tutorial Part 2

• For turnin script, prep cs141s when you log in. Please put all your partners names and IDs in the README file. Following are the instruction for turnin
  • Usage: tar-command | turnin -c courseid
    Example: tar cvf - LoginNameLab2.dir | turnin -c cs141s

  Where "LoginNameLab2.dir" has all the files that you need to turnin. Please start your directory namewith the login name of the account you are using to turnin the assignment. This will include README, all the code files, .imi files etc.

  More detailed instruction about turnin can also be found at http://acs.ucsd.edu/info/turnin.php

Projects:

Lecture:

Lecture for CSE 141L is scheduled for Tuesday from 6:30 PM - 7:50 PM in Center 115.

Lecture Notes:

Lecture 1 - ISA

Lecture 2 - ISS

Lecture 3 - Datapath

Lecture 4 - 8 bit Processor

TA Contact Information and Office Hours:

All office hours for the CSE 141L TAs are held in AP&M 2444.

Note: For the first week of classes, there will be no office hours for 141L.

CSE 141 Homepage : Link to the theory course.