A simulator accepts inputs that you specify and displays what the design's anticipated outputs will be. In this tutorial, we will be doing rtl-level simulation, where rtl is an acronym for register transfer level, in which the input to the simulator is the compiled Verilog HDL source code. Verilog HDL is a programming language for defining the structural and behavioral description of digital circuits. In rtl-level simulation, since no delay information is present, the simulation has no delays in it. The simulator that you will be using is the ModelSim simulator, which is available in the Mentor Graphics toolset.
Synthesis is the process of taking human-readable input such as Verilog HDL source code files and creating a low-level description which describes the design in terms of simple gates. The synthesis tool you will be using is Synopsys. A TSMC (Taiwan Semiconductor Manufacturing Corporation) ASIC (application-specific integrated circuit) library will be used in Synopsys.
Verilog source code is plain text contained in a single file or a group of files. Verilog text files use the file extension, .v .
The testbench module in
In Modelsim vsim,
You may want to occasionally print
out the simulation results that appear in the wave window. You can use the zoom feature from the wave menu to obtain the proper zoom. To print the wave, from the wave menu, select File | Print Postscript... When the Write Postscript window opens, click File name:
and type in a name for the file name, i.e., Note: Simulation can also be performed on the output of the
synthesis tool. This is called gate level simulation as opposed to
rtl level simulation performed in this tutorial. Gate level simulation
is more accurate, but takes longer than rtl level simulation.
Gate level simulation will not be performed in this tutorial.
The Verilog description
of a 4-bit adder using a process with a sensitivity list is
p4ba.v. The sensitivity list is to the right of always@.
Signals that are read in the always construct should be placed in the sensitivity list.
Since the signals, addend_one, addend_two, and carry_in are read in the process, they are included in the sensitivity list.
Whenever one of the signals in the sensitivity list changes value, the always block will be executed.
The assignment statements in the unclocked process use the blocking assignment operator, =.
Signals written to with the blocking assignment operator are updated instantaneously.
Combinational logic (unclocked always block) should be described using the blocking assignment operator.
The other type of Verilog assignment operator is the non-blocking assignment operator, <=. When a signal is written to with the non-blocking assignment operator, it is scheduled to be assigned the new value at the end of the current time unit. Sequential logic (clocked always block) should be described using the nonblocking assignment operator. In the Verilog module, sum, carry_out, and carry are declared to be of type reg
because they are assigned to in the always block. No registers will be synthesized as no edge is specified in the event specification list (sensitivity list).
A sample Verilog testbench for the moore state machine is provided:
tb_moore.v.
Suppose that you want to view on the wave timing diagram the six signals: RESET, X, CLK, Z, NEXT_STATE,
and CURRENT_STATE. A synthesis script file for the moore state machine is
moore.scr.
5 Synthesis: Synopsys
Your working directory should
be ~
Cell, area, and timing reports for the hierarchical four-bit adder will be written
to the files, h4ba_cells, h4ba_area, and h4ba_timing.
6 4-bit Adder using an always block example
Processes in Verilog are modeled with
the always block.
In hardware description languages, processes are sections of sequentially executed statements,
as opposed to the dataflow environment, where all statements are executed
concurrently. In a process, the order of the statements does matter. In
fact, processes resemble the sequential coding style of high level programming
languages. Also, processes offer a variety of powerful statements and constructs
that make them very suitable for high level behavioral descriptions.
7 FSMs
One method to do this is to use a .do macro file. Another method is to use the window menus.
8 Counter example
9 Register File example
A four 32-bit register file example is reg4.v. To read a register, the nr_w bit is set to 0; to write to a register, the nr_w bit is set to 1. The register to be read from or written to is determined by a 2-bit address.
The register file module in
reg4.v uses four instantiations of the 32-bit register module in the Verilog source,
reg.v.
10 A few notes