module tb_moore;    // Verilog tb for moore state machine    
   reg reset_wire;
   reg clk_wire;
   reg x_wire;
   wire z_wire;

   moore uut  (                        
               .RESET(reset_wire),     // instantiation of state machine
               .X(x_wire),             // with explicit port mapping 
               .CLK(clk_wire),        
               .Z(z_wire)
              );
   
   initial
      begin
         clk_wire = 0;
         forever #10 clk_wire = ~clk_wire;      // create clock
      end

   initial  
      begin
         reset_wire = 1;
         x_wire = 0;
         # 5;
         reset_wire = 0;
         x_wire = 1;
         # 20;
         x_wire = 0;
         # 20;
         x_wire = 1;
         # 60;
      end 

endmodule