module tb_h4ba;            // Verilog tb to test hierarchical four-bit adder.
   reg [3:0] addend_one;                         
   reg [3:0] addend_two;
   reg carry_in;
   wire [3:0] sum;
   wire carry_out;
                                                   // instantiation and port mapping 
   h_4_bit_adder uut (                           // .formal(actual)   
                     .addend_one(addend_one),
                     .addend_two(addend_two),
                     .carry_in(carry_in),
                     .sum(sum),
                     .carry_out(carry_out)
                     );

   initial
      begin
         carry_in = 1'b0;                  // carry_in = 0
         addend_one = 4'b1010;              // addend_one = 10 
         addend_two = 4'b0011;             // addend_two = 3       
         # 15                              // sum = 13; 15 ns
         carry_in = 1'b1;                  // carry_in = 1
         # 15                             // sum = 14; 30 ns
         addend_one = 4'b0010;            // addend_one = 2
         addend_two = 4'b1111;            // addend_two = 15      
      end                                // sum = 1; carry_out = 1; 45 ns

endmodule // tb_h4ba