/* read in source code and check for errors */
read -format verilog moore.v 
/* The hdl source code is mapped and optimized to cells from the technology library */
compile -map_effort medium
/* set_fsm_state_vector is used to identify the flip-flops in the design which hold the current state of the fsm */
set_fsm_state_vector {CURRENT_STATE_reg[0],CURRENT_STATE_reg[1],CURRENT_STATE_reg[2],CURRENT_STATE_reg[3]}
/* group the flips flops and their associated combinational logic into a separate level of hierarchy to help isolate the fsm from the rest of the design */
group -fsm -design_name fsm_MOORE
current_design=MOORE
set_fsm_encoding_style one_hot
set_fsm_encoding {"s0=2#0001" "s1=2#0010" "s2=2#0100" "s3=2#1000"}
extract
/* set_fsm_minimize is a switch that when turned on prior to compile, the tool infers the minimum number of states required for the fsm */
set_fsm_minimize true
compile -map_effort medium
/* write reports to file */
report_area > moore_area_report
report_timing > moore_timing_report
report_cell > moore_cell_report
report_fsm > moore_fsm_report