/* The source code is read in and checked for errors using the read command. */
read -format verilog full_adder.v
read -format verilog h_4_bit_adder.v
/* uniquify removes multiply-instantiated hierarchy in the design by creating a unique design for each cell instance. */ 
uniquify -force 
/* The design is optimized and mapped to the technology library using the compile command. */
compile
/* The cell, area, and delay reports are written to files using report_cell, report_area, and report_timing commands. */
report_cell > h4ba_cells
report_area > h4ba_area
report_timing > h4ba_timing