evaluation

Vagelis Hristidis (vagelis@cs.ucsd.edu)
Thu, 25 May 2000 02:25:56 -0700

The Multics Virtual Memory: Concepts and Design

This paper describes the virtual memory of Multics. It uses segmentation and
paging hardware to implement a large, segmented main memory where all
information resides. The processor can address directly memory. Control
access is made easier with segmentation . Access in main memory is also
controlled. Paging is used within the segments to simplify space allocation.
The supervisor is also using segment addressing.
Segmentation incurs fragmentation and compaction is needed, which is a
serious problem for the system performance. It also seems to me that pure
paging is the current trend in OS's because of its simplicity. The fact that
the supervisor is also using segment addressing may degrade the performance
of the system and also the robustness.

Machine-Independent Virtual Memory Management for Paged Uniprocessor and
Multiprocessor Architectures

This paper describes a virtual memory model that aims in separation of
memory management from hardware support. Of course , it sounds unrealistic
that the system performance does not degrade , since exploiting some
hardware features can enhance the overall performance. Not much is said
about per-user access control of memory pages. Furthermore the shadow
objects technique is not desirable in all applications(eg when locking is
desired like in databases).
Also, the association of a pager with each memory object seems to degrade
performance compared to a central page fault handling mechanism.