eval14.txt

Yu Xu (yxu@cs.ucsd.edu)
Thu, 25 May 2000 01:22:54 -0700

Evaluation of " The Multics Virtual Memory: Concepts and Design"


In Multics segmentation provides a generalized basis for the direct
accessing and sharing of online information. It has two nice design goals:
(1) it must be possible for all on-line information stored in the system
to be addressed directly by a processor and hence referenced directly by any
computation; (2) it must be possible to control access, at each reference, to
all on-line informant in the system.
The advantage of directly addressibility is that information copying is
no longer mandatory. To control access, the basic idea is that each segment
is associated with a set of access attributes for each user who may access
the segment and these attributes are checked by hardware upon each segment
reference by any user. Segment attribute are stored in special segments
called directories, which are organized into a tree structure.
There are several features in Multics segmentation:
(1) the number of segment descriptors available to each computation is
sufficiently large to provide a segment descriptor for each file that the
user program needs to reference in most applications.
(2) Multics provides for segments of sufficient maximum size so that only
a few of can be entirely core-resident at any one time. The segments can grow
from any initial size smaller than the maximum permissible size.
(3) supervisor itself is segmented and runs in the address space of each
user process. The advantages include the supervisor use the same conventions
that are used in user programs and that some supervisory facilities provided
for the management of user segments can also be applied to supervisor
segments.
(4) Segment fault and page fault are handled by segment fault handler and
page fault handler separately.


Two questions about this paper:
This paper doesn't talk about how do they organize the access attributes
associated with each segment efficiently. Because each reference to a
segment is checked by hardware, this may be a big performance issue.
Their virtual memory system is built on Honeywell 645 segmentation and
paging hardware. They don't mention the portability. I think it's not easy
for their implementation.





Evaluation of "Machine-Independent Virtual Memory Management for Paged
Uniprocessor and Multiprocessor Architectures"


The main feature of Mach virtual memory system is the separation of
software memory management from hardware support.
The primary requirement of memory management hardware is an ability to
handle and recover from page faults. Mach supports : large, sparse virtual
address spaces, copy-on-write virtual copy operations, copy-on-write and
read-on-write memory sharing between tasks, memory mapped files and user
provided backing store objects and pagers.
There are five basic abstractions in Mach: Task, thread, port, message and
memory object.
Four basic memory management data structures are used in Mach:
the resident page table, the address map, the memory object, the pmap.
A feature of Mach is that a Mach physical page does not correspond to a
page as defined by the memory mapping hardware of a particular computer. The
size of a Mach page is a boot time system parameter. This is really flexible.
The interface between machine-independent memory management and
machine-dependent modules has been kept relatively small and the implementor
of pmap needs to know very little about the way Mach functions. This is
really good software engineering decision. Mach is easily ported onto several
different hardwires and still has good performance.