This lecture covered number representations, the related-base-change algorithm, and touched on RISC and CISC instruction designs.

Polynomial representation of a number: in base 10, the number
`n` = 524398, denoted 524398_{(10)} equals 5 *
10^{5} + 2 * 10^{4} + 4 * 10^{3} + 3 *
10^{2} + 9 * 10^{1} + 8 * 10^{0}. Suppose I
want to express this same number in base 2. The ``ones'' binary
digit (or bit) can be determined as follows: we write `n` =
`m`_{1} * 2 + `n`_{0}. We get
`n`_{0} = 0, and `m`_{1} = 262199. We
write `m`_{1} = `m`_{2} * 2 +
`n`_{1, and get n1 = 1 and
m2 = 131099. Repeated division by the base and
writing the remainder down (in reverse order) gives 1000 0000 0000
0110 1110 (2).
}

That was the general algorithm for getting the representation of a
number in a different base. If the original and destination bases are
related, however, we can do better. Suppose we have

`n` =
`d`_{2} * `B`^{2} +
`d`_{1} * `B`^{1} +
`d`_{0} * `B`^{0}

where
`d`_{i} are the digits of the number `n` in base
`B`. Suppose we have (lowercase) `b` where `B` =
`b`^{2}, and we wish to write down `n` in base
`b`. Well, each digit `d`_{i} is in the range
0, ..., B-1, and can be written as a two base-`b` digit number
`c`_{2i+1} * `b` + `c`_{2i}.
Thus,

`n` =
`d`_{2} * `B`^{2} +
`d`_{1} * `B`^{1} +
`d`_{0} * `B`^{0}

=
(`c`_{5} * `b` + `c`_{4}) * `B`^{2} +
(`c`_{3} * `b` + `c`_{2}) * `B`^{1} +
(`c`_{1} * `b` + `c`_{0}) * `B`^{0}

=
(`c`_{5} * `b` + `c`_{4}) * `b`^{4} +
(`c`_{3} * `b` + `c`_{2}) * `b`^{2} +
(`c`_{1} * `b` + `c`_{0}) * `b`^{0}

=
`c`_{5} * `b`^{5} + `c`_{4} * `b`^{4} +
`c`_{3} * `b`^{3} + `c`_{2} * `b`^{2} +
`c`_{1} * `b`^{1} + `c`_{0} * `b`^{0}

Thus, each base `B` digit turned into two base `b`
digits. Doing the reverse conversion, of course, would involve
grouping two base `b` digits together to form a base `B`
digit.

**Assignment**: perform the following base conversions.

- 387
_{(10)}= ?_{(3)} - 78354
_{(9)}= ?_{(3)} - F786
_{(16)}= ?_{(8)} - 12112
_{(3)}= ?_{(9)}**There was a typo here.**

Due before class next Wednesday. Expect to see a question on this on the midterm.

Missing from this web page: design philosophy behind RISC. Time to complete instructions. Clock cycle times. Simple instructions finish fast, complex ones take longer. Some CISCy computers (e.g. VAX) had instructions that no compiler knew how to generate. Profiling programs to get dynamic execution traces. Optimal use of chip real estate. More registers in RISCs. Instruction density and memory bandwidth.

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