# CSE 30 -- Lecture 10 -- Oct 30

Assignment 4 was due at the beginning of this class; I extended the maximum late days to 4 from the usual 2 for this assignment, and lowered the lateness penalty to 5% of the grade per day instead of the usual 10%.

In this lecture I talked about data and control flow hazards and how they cause {\em bubbles} in the pipeline.

To understand data hazards, think about pipeline stalls that must occur in order to wait for a register to receive its value from a previous operation, e.g.,

	mult $t0,$a0
mflo $t0 add$t0,$t0,$t1

The mflo instruction needs to access the \$lo register, which is one of the destinations of the mult instruction. Because the mult instruction is especially slow (10-18 cycles, depending on the processor), the mflo must wait until mult is complete before it move through the instruction pipeline.

To understand control flow hazards, think about the problem of pipelining conditional branches. The point of pipelining is to have simultaneous execution of a sequence of instructions, so that as an instruction finishes its current stage, it may be passed onto the next stage in the pipeline. The sequence of instructions in the pipeline, of course, are all at different stages of execution. If a conditional branch occurs in the instruction stream, which is the next instruction to follow the branch is unclear: it depends on which way the branch is going to go.

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