# CSE 140 Syllabus

## Textbooks

Following are the suggested texts for this course :

• [Harris]: “Digital Design and Computer Architecture” by David Harris and Sarah L. Harris
• [Lang]: “Digital Systems and Hardware/Firmware Algorithms” by Milos D. Ercegovac and Tomas Lang

Your final grade for the course will be based on the following weights:

• 5% Class Participation
• 4% Homework
• 30% Midterm 1 (T 10/28/14)
• 30% Midterm 2 (T 11/18/14)
• 30% Midterm 3 (Th 12/11/14)
• 1% Final Exam (Take home due 230PM, F 12/19/14)

To pass (C- or better) you need to get at least 45% overall.

## Schedule

1 Course Overview - The digital abstraction and basic logic gates
[pdf] [ppt]
[Harris] Chapter 1
2 Combinational Logic: Truth tables, Boolean Algebra, Axioms - DeMorgan's, Consensus, Covering, Shannon expansion, Boolean Equations (sum of products, product of sums), reduction of boolean expressions using boolean algebra
[pdf] [ppt]
[video on SOP & POS]
[Harris] Chapter 2, Section 2.1-2.4
3 Combinational Circuits: Hardware reduction, bubble pushing, 2 variable K-maps
[pdf] [pptx]
[Harris] Chapter 2, Section 2.5, 2.7
4 Optimizing Combinational Circuits: Logic minimization with multivariable K-maps, Handling don't cares, prime and essential prime implicants and implicates
[pdf] [ppt]
[video on basic Kmap] [video on finding all solutions from Kmap]
[Harris] Chapter 2, Section 2.7
5 K-Maps in higher dimensions, K-map to product of sum minimization
[pdf] [ppt]
6 Universal Gates, Universal sets with NAND, NOR and XOR gates, block diagram transfers
[pdf] [ppt]
7 Sequential Network Components: Bistable memory elements, latches, flip flops (SR, D, T, JK) and registers
[pdf] [ppt]
[video on D Latch/FF] [video on SR & JK]
[Harris] Chapter 3, Section 3.1, 3.2
8 Sequential Network Specification: Finite State Machines
[pdf] [pptx]
[Harris] Chapter 3, Section 3.3, 3.4.1, 3.4.2
9 Sequential Network Implementation: Moore and Mealy Machines
[pdf] [ppt]
[video on implementing JK using T] [video on implementing X using Y]
[Harris] Chapter 3, Section 3.4
10 Sequential Network Timing Analysis
[pdf] [ppt]
[video on Timing analysis]
[Harris] Chapter 3, Section 3.5
11 Standard Combinational Modules: Decoders Encoders, Multiplexer, Demultiplxer, Adders and etc.
[Decoders and Encoders, pdf] [ppt] [Multiplexers and etc., pdf] [ppt]
[video on Mux part 1] [video on Mux part 2]