CSE 141L -- Computer Architecture Lab
Fall 2013, Instructor: Dean Tullsen
Announcement -- we will be meeting the first day for lab (9 am).
Related Web Page:
141 home page)
Basic Course Information:
TA: Raymond Paseman
- CSE 3216
- tullsen at cs dot ucsd dot edu
- office hours: Tu 4-5, Th 11-12
TA: German Alfaro Ibarra
- office hours: Tu 5-6:30, Th 5-6:30
- room: CSE B250
- rpaseman at eng dot ucsd dot edu
Meeting time and place
- office hours: M 5-6, W 11-12, Th 3-4
- room: CSE B250
- gealfaro at eng dot ucsd dot edu
Course textbooks and tools
Center Hall 212, F 9-9:50 (rarely)
Center Hall 214, F 3-3:50 (usually)
There is no textbook for the class, but you will
find the CSE 141 textbook helpful in many ways during the lab.
Patterson & Hennessy, "Computer Organization
and Design -- The Hardware/Software Interface", Morgan Kaufmann, Fourth
may also find some of these very helpful, especially the Processor
Synthesis Lectures on Computer Architecture
The lab will utilize, for some of the lab assignments,
the Altera Quartus II Web Edition tools.
You can dowload a free version here. It should also be available in the lab.
Labs will typically be due two weeks after they are
Piazza for class mailings and discussion boards
Everyone in the class is expected to be on Piazza. Please sign up (if not already)
here: sign up, and access the course
- The grade for 141L will be based primarily on 4 lab
reports. I expect that most students will complete the lab assignments
as specified; thus, the quality of the lab reports will likely be the most
important factor in determining grades. Attendance will also be factored
into grades (in a major way) somehow. Attendance at four of the labs (when we discuss a new lab assignment), in particular, is absolutely mandatory.
- Late assignments are not encouraged. All lab reports
are due at the beginning of class on Friday. Anything else is considered
late. You will have one grace weekend during the quarter. I.e., you
can turn one assignment in late, as long as it is in my office (under the
door) before 9 a.m. on Monday. I recommend not spending that grace time
frivolously early in the quarter. After you have spent your grace weekend,
late assignments will be accepted, but with significant penalties. We will
make every effort to return assignments to you in a timely manner -- limiting
your ability to turn things in late is, unfortunately, critical to that goal.
- All 4 lab reports are required. You must do
a credible job on each to pass the class.
- We will use gradesource to record lab grades. This will not be a tool to estimate your final grade, etc. It is only there so you can check that we have entered your grades correctly. Please do so -- we don't want to make mistakes. We will use Piazza to post lab assignments and to host discussion boards on various topics.
Cheating WILL be taken seriously. It is not fair
to honest students to take cheating lightly, nor is it fair to the cheater
to let him/her go on thinking that is a reasonable alternative in life.
Don't test me on this one.
The following is not considered cheating:
- discussing the tools or logic design techniques
with other groups.
The following is:
-Copying lab designs from someone who is not
your partner, or lab report text from anyone.
-Viewing lab designs or lab reports from
anyone who is not your partner, including those who have taken the class
in previous years.
-Altering timing data produced by Altera, e.g.
to make a non-working design appear to be working.
- Penalties -- anyone copying information or having
information copied on a lab, or any other violation of class policy,
will receive an F in the class and will not
be allowed to drop. They will be reported to their college dean.
- There will be 4 lab assignments. Each will require
a written report. There will be no midterms or final associated with this
class. The final grade will be determined by the quality of the lab reports
and the completeness and quality of the lab work (as demonstrated in the
- Some but not all of the labs will require the Altera
tools, which everyone should be familiar with. If you are not, you must take some time the first two weeks to familiarize yourself with it. After that, it will be too late -- you need to be ready to run at that point.
- The labs can be done in groups
of 1 to 3. Lab reports are to be done collaboratively with your fellow
group members, except when specifically instructed otherwise. Changing,
splitting, merging of groups is only to be done with the permission of
the instructor, and such permission is typically not given.
Verilog Resources: (seriously needs to be updated)
Verilog Overview/tutorial by Sat Garcia
Verilog Fundamentals by Krste Asanovic at MIT
Verilog Design Examples by Krste Asanovic at MIT (synthesis friendly)
At some point, we will attempt to synthesize our circuits (e.g., to extract timing). These resources were selected because they should all be synthesis friendly. Many tutorials and verilog code available on the internet are not.
- Altera tools are available in CSE B240 and CSE B250. Not sure what version or how up to date. If you go and find out, please let me know.
If you have comments or suggestions, email me at
tullsen at cs dot ucsd dot edu