| Date | Description |
| 30-Sep-12 | Original posting |
On Bang (as well as most other Linux systems)
the lscpu command reports
the processor's memory hierarchy. Note that for shared
private
caches (such as L1 and L2) you need to multiply the
reported cache size by the number of cores, to obtain the total cache size
at a given level. The output doesn't tell you which caches
are duplicated, so you'll need to dig deeper to get this information .
In addition to the lscpu command, there is also a file called /proc/cpuinfo, which provides a variety of other information. For example, here is part of Bang's cpuinfo file:
cpu family : 6 model : 15 model name : Intel(R) Xeon(R) CPU E5345 @ 2.33GHz stepping : 7 cpu MHz : 2333.331
The contents of cpuinfo enables you to identify the specific processor, and the identifying information may be used to obtain other details from on-line resources. This information confirms that a Bang node contains quad-core 2.33GHz Intel Xeon E5345 processor. There is additional information in procinfo: family, model, and stepping. So in this case the family is 6, the model is 16, and the stepping is 7. This will allow you to explore smaller scale changes to the processor’s design that occurred over time.
We may learn more by accessing Intel's ARK Database. Once at the ARK web site, search on "E5345" in the search window at the top of the page. You'll obtain various information; for example, the processor has 4 cores, and a 8 MB unified (instructions + data) L2 cache shared among all cores. (The 2.33 GHz clock speed matches that listed in the cpuinfo file). The L1 cache size, not listed, is 32KB per core; separate instruction and data caches.
Unfortunately, Intel dropped the handy processor finder web site (CPU World maintains similar functionality if you know the S-Number). However, you may obtain more detailed information about the processor in another way. There is set of files providing detailed characteristics of all levels of cache (though there are many files):
/sys/devices/system/cpu/cpu*/cache/index*/*
This information further verifies that each pair of cores shares 4MB of L2 cache.
To learn more about the Nehalem processor consult one of the following sources
More generally, the definitive source of information about Intel processors Intel 64 and IA-32 Architectures Optimization Reference Manual, (June 2011), where you can find detailed information about your processor.
This document is accessible from another page that Intel maintains with pointers to a several documents on Intel 64 and IA-32 Architectures Software Developer Manuals
Intel also publishes a Quick Reference Guide for the many available compiler options.
As mentioned in class, Lilliput has a 4MB L3 cache. The other Intel boxes (cseclass 03-06) have an 8 MB cache. The AMD boxes (cseclass 01-02), with Phenom II X6 1090T Processors, have a 6MB L3 (Each core also has a 512KB L2 cache, for a total of 3MB) Here is a comparison of different Phenom processors and here is a summary of basic architectural features.You can find more information at the AMD Developer site
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[Sun Sep 30 20:57:13 PDT 2012]