cse141L Lab 1: Be a Hardware Hacker!


Changelog

October 5

To ensure that your reports will be submitted correctly, besides sending them through e-mail also bring a hard copy in class.

October 3

Removed the link to verilog tutorial slides. Use the slides from class instead, they are consistent with our coding standards.

September 30

Send an email to the TA with a "code-name" of your choice to be used instead of your personal info for the Grade-sheet (your code-name should not under any circumstances reveal your identity). The subject line of your email should read "[CSE141L] LastName, FirstName CODENAME: my_codename".


Part 1: Log into the discussion board

Due: October 7

There is a link to the course's discussion board on the course homepage. Your login is your official UCSD user name (i.e., your @ucsd.edu email address without the "@ucsd.edu" part). Password is the same as the one you use to access your university email account(AD password).

Take some time to explore the discussion boards features.

Reading the blackboard is mandatory. It is the only place that all announcement related to class will be posted.

Need an account? If you are enrolled through concurrent enrollment or, for some other reason do not have an account, email Vasileios with your preferred username and he will create an account for you.

Deliverable

  • Post a reply under the "Welcome" message in the administrative forum. You don't need to hand anything in. If you are enrolled in 141 as well, you only need to post once.
  • Due: October 7

    Part 2:

    Due: October 7

    Lab 1 is a preparation stage for future labs, and consists of two parts - Xilinx ISE and Verilog. In Lab 1, you will install Xilinx ISE and follow a step-by-step tutorial to learn essential concepts and working flow in hardware designs. For those who used Xilinx ISE in 140L, this lab should be very easy. Otherwise, you should START NOW - there might be many unexpected problems. If you have any question regarding this lab, please post it on the blackboard.

    Tools:

  • Get Xilinx WebPack 10.1. It should already be installed in the labs. For personal use (laptops, home desktops etc.):
  • On this link click on "Download ISE WebPACK" from the Quick links.
  • If you already have an account with Xilinx, put your username and password. Otherwise, click on Create Account. Enter a username, password, email of your choice. You will soon receive an email from Xilinx for the activation of your account. As soon as you get the email, follow the instructions and log in to the Xilinx website.
  • You will reach a webpage as the one shown below. YOU WANT VERSION 10.1, NOT 11.1 , so click on the link as instructed in the screen-shot.
  • Following you can click on "+ -- Download Files Individually" and then "Download". Your browser should allow the pop-up window to appear. The tool is about 2.25GB. Using the university wireless connection took ~40mins. You probably want to use high speed internet or leave it downloading for a few hours while you sleep. Also remember the Registration ID since you will need it later.
  • Extract the downloaded file and run setup to install the Webpack(we recommend Windows platforms). Enter the Registration ID and finish the installation.
  • MAKE SURE YOU DOWNLOAD THE LATEST UPDATES, otherwise you might run into some very weird tool behaviors. Note: you will be using version 10.1, but many of the screen-shots in this lab and other labs may be of a slightly older version--so what you see may be a little different than what is pictured here.
  • Xilinx Quick Tutorial

    Xilinx provides a good step-by-step tutorial. With this tutorial, you will be able to learn how to perform various activities in the hardware design process. It should take less than two hours to follow the tutorial.

    A Simple 8 bit Adder

    Now that you know how to use Xilinx ISE, we will examine a few aspects of hardware design. For more information, I highly recommend you skim through chapter 2 and chapter 5 of Xilinx In-depth Tutorial.

    32 bit Adder

    Multiplier

    Free Form Experiment

    Useful Resources

    Deliverable

    • No lab interview for lab 1. In future labs, you will have interview sessions with a TA to show your results.
    • Submit your report for the questions above to the TA via e-mail by the due date before the beginning of the class. Also bring a hard copy or your report in class.
      • Answer all of the questions (10) found in the lab description.
      • The report should be in a single PDF file (including answers to questions, verilog source code, graphs, screen-shots, etc). There are many tools out there capable of integrating text and graphics and producing PDF files (OpenOffice does a pretty good job).
      • Name your PDF file cse141L-lab1-LastName-FirstName.pdf with your last name and first name substituted for LastName and FirstName, respectively.
      • The subject line of your email should read "[CSE141L] Lab 1 Submission - LastName, FirstName".

    Due: October 7