Office: EBU3B 3212
Office Hours: Tuesday 5-6pm, in CSE basement B-230,B-240 (and by appointment)
Teaching AssistantVasileios Kontorinis
Office Hours: Thursday 5-8pm in CSE basement B-230,B-240
Course discussion board: cse141L. Required reading. Get signed up.
This is the laboratory class associated with cse141: Introduction to Computer Architecture. Over the course of the quarter, you will design a processor that implements an instruction set of your own design. It will provide you the chance to grapple first-hand with the issues of processor design.
There are two ways to get an "A" in this class. One is to implement a working processor by the end of the quarter that executes programs in an ISA of your design. This is the grading option you should strive for.
The other way is to do well on the labs. If your processor doesn't turn out as well, I will consider your performance on the labs and participation (see below). Your grade will be at least the maximum of the "your processor works" grade and the lab assignment grade.
In addition to the labs, you should be an active contributer to the web board. The tools are challenging and sometimes buggy. Your classmates (in addition to the course's staff) are an excellent resource for help with the tools.
This class is about
Calculating grades I compute the lab grades (for the second of the above two options) using an Excel spread sheet. In the interests of transparency, the current grade sheet (with identifying information removed) is available here. The grade sheet contains all the information about curves and how the grades are computed. It is somewhat sophisticated, if you find bugs please bring them to my attention.
Late lab write ups If you cannot complete you lab on time, you can turn it in late, but your grade will be penalized. The penalty is one letter grade per 24 hours extension. Up to 2 extensions are possible. For example, if the labs are due at 5pm, you have until 5pm the next day to turn it in with one letter grade penalty, and until 5pm the day after to turn it in with a two letter grade penalty, and so on.
|Labs||84%||There are six labs of equal weight.|
|Class and Blackboard participation.||16%||This includes speaking up in class, helping other folks in the lab, and posting to the Blackboard.|
Items in the schedule more that one week in the future are subject to
change. Check back for updates for the assigned readings, etc. The date
for the midterm will not change, however. Nor will deadlines for
I will post the slides for most lectures. Since the slides contain material I am not allowed to distribute publically, they are only available from on campus or via the campus proxy. Instructions for setting up the proxy can be found here. Using the proxy is useful in general, since it gives you full access to the libraries and other resources from off campus.
|Wednesday, September 30||Administrivia; Overview of the course; Lab 1 assigned; Verilog I||
|Wednesday, October 7||Verilog II; datapath and control design. Lab 2 preview.||
|Project 1-1; Project 1-2;|
|Wednesday, October 14||Verilog II; datapath and crontrol design; Lab 3 preview.||04_ControlAndLab3.pdf||Project 2;|
|Wednesday, October 21||Lab 4 preview||Project 3;|
|Wednesday, October 28||Lab questions|
|Wednesday, November 4||Lab 5 preview||Project 4;|
|Wednesday, November 11|
|Wednesday, November 18||No class||Project 5;|
|Wednesday, November 25|
|Wednesday, December 3||Lab questions/CAPE|
|Friday, December 4||Lab 6 Due||Project 6;|
|Wednesday, December 10||Final|