Follow this link to the CSE 140 Webpage

CSE 140L Fall 2009 

(Mondays: 5:00 - 5:50pm, EBU3b 2154)

 

Instructor:

Alex Orailoglu, alex@cs.ucsd.edu

Office Hours: Tuesdays 2:30 – 3:30 PM and Wednesdays 3:30 – 4:30 PM; EBU3B 3134

 

Teaching Assistants

Mingjing Chen

mjchen@cs.ucsd.edu

Office Hours:

Thursdays 8:00pm-10:00pm

EBU3B B240A

Jeff Lu

j6lu@ucsd.edu

Lab Hours:

Wednesdays 7:30 – 9:30 PM;

EBU3B B240A

Announcements:
*Please check back frequently to see the updated announcements.

*Change of classroom: starting from 10/5/2009, the classroom for CSE140L will be changed to EBU3b 2154

 

* To help you prepare for the second midterm of CSE140, the 140 discussion section on Wednesday (11/04) and the 140L lecture on Monday (11/02) will be exchanged.

 

*About assignment submission on WebCT

You can change the file you have already submitted before deadline. What you should do is to go to assignment--->submitted--->Lab *--->click the taken back icon beside the "status" (an icon of a hand taking a file back). Then you can resubmit your file.

*You are allowed to work in groups of 2. While submitting your files on WebCT, submit from only one account but make sure you include your partner’s name and also his/her WebCT account name in the report.

*Please read the tutorial on how to turn your projects
 Link to WebCT: http://webct.ucsd.edu/

*Here's a tutorial for LogicWorks

                 LogicWorks review

 

*For those of you who need a quick functional review of basic circuits, please read the "Review of simple circuits" handout

 

Handouts:
  1. Course Info
  2. Course Policy
  3. Review of simple circuits
  4. Multiplication algorithms

 

 

Final exam:

12/10/2009, 7:00 PM - 9:59 PM

 

 

 

Evaluation:

 

%

Labs 1,2

10%

Labs 3-5

20%

Final

20%

Labs:

Lab 1    Due Oct 9, Friday, 3:00pm

 

Component library for Lab 1    Lab1Lib.clf

 

* The component library we provide to you contains the components you may need in your design. Add it into your LogicWorks library so as to make use of it. You may also need to use the components in the standard library provided by LogicWorks.

 

Labs:

Lab 2    Due Oct 23, Friday, 3:00pm

 

Component library for Lab 2    Lab2Lib.clf

 

 

 

Labs:

Lab 3    Due Nov 6, Friday, 3:00pm

 

Component library for Lab 3    Lab3Lib.clf

 

Sample circuit for Lab 2

 

 

Labs:

Lab 4    Due Nov 20, Friday, 3:00pm

 

Component library for Lab 4    Lab4Lib.clf

 

When calculating X-to-S and Y-to-S delays, only count the delays from input (X or Y) to the binary sum.  No need to further consider the delays of the invalid-pattern detection logic and the correction circuitry.