Lab 3 and Lab 3A. 10-bit CPU. Instructions for building a RAM in Xilinx. This includes code to
initialize the RAM to the correct start values. If you have trouble with the VHDL code for the RAM, try these files to do it in Verilog: DataRAM.v and dataram_init.list.
Lab 4-- Cache Simulation. You will need the following traces: art, crafty, and eon. You may also find the following C program very useful cachesim.c.