Please Note:  All homework assignments must be typed, unless otherwise specified.

Please make sure you understand the class integrity poliy before you begin doing any of the homeworks!

Homework Assignments:

• Homework #1 -- Due Tuesday, October 3.
  • P&H 2.2, 2.4, 2.9, 2.14, 2.30, 2.32, 2.34, 2.37 (just rows 1, 4, 6, 7, 10, 11)
• Homework #2 -- Due Thursday, October 12
  • P&H 4.1, 4.7, 4.9, 4.11, 4.12, 4.17, 4.10, P1, 3.2, 3.5, 3.7, 3.10
  • P1: Machine B runs at 2 GHz and has a CPI of 1.3 for a particular program. Machine C, which runs at 5 GHz, has a CPI of 2.4 for that program, while executing 20% more instructions. Which machine is faster? What is the speedup over the slower machine?
• Homework #3 -- Due Tuesday, October 24
  • P&H 3.34, 5.2a,b,c,f, 5.8, 5.10, 5.21, P2, P3, 5.37*
  • * use the following frequencies (loads 26%, stores 11%, reg-reg ALU 44%, branch 16%, jump 3%)
  • P2 -- Give an example of one Intel IA32 instruction that could not be implemented on a single-cycle processor, assuming reg file and memory elements similar to what we used in class.
  • P3 -- This is the same as 5.32, except solve it for the instruction "subi". Show changes, if necessary, to the datapath and control FSM.
  • these might be useful, fig 5.17, fig 5.28, and fig 5.38.
• Homework #4 -- Due October 31, but can be turned in Nov 2. But do the problems before the midterm.
  • P&H 5.41, 5.47, 6.1*, 6.4, P4, W1
  • *as in the example in the book, just assume all lw instructions, for simplicity.
  • P4 -- using figure 6.41 as a template, highlight all data paths active (active means carrying data that will actually be used to complete the instruction) for the following code, in the cycle that the lw is in the wb stage:
    • lw $5, 1000($4)
    • add $1, $3, $5
    • sw $10, 1004($4)
    • sub $3, $10, $1
  • W1 -- Using the web, find the number of pipeline stages for the following processors: Intel Pentium 4, Intel Core 2 Duo, AMD Opteron, Intel Itanium 2.
• Homework #5 -- Due November 14.
  • P&H 6.2c, 6.14 (use figure 6.32, not 6.30, but also refer to 6.27 for the control signals), 6.18, 6.26, 6.36, P5, P6
  • P5 -- Circle all of the instructions in the following code that could safely be moved into the branch delay slot (replacing the nop). Assume other instructions cannot be reordered or changed. Assume you know nothing about the missing code (the ...).

    add R1, R2, R3
    sub R5, R2, R3
    and R7, R5, R2
    lw R8, 1000(R5)
    beq R7, r15, label:
    nop
    add R6, R7, R5
    sub R5, R7, R5
    lw R9, 2000(R2)
    ...
    label: add R9, R7, R5
    addi R5, R0, #0
    ...

  • P6 -- Show forwarding and stalls for the following code, assuming the pipelined machine from figure 6.36. Show it the way we did in class, with IF ID EX M WB, and arrows and bubbles.

    lw R3, 100(R5)
    add R6, R3, R2
    sub R9, R3, R8
    lw R1, 2000(R9)
    add R5, R4, R3
    subi R7, R1, #8

• Homework #6 -- Due November 21
  • P&H 6.35, 6.47 (note 1), P7, 7.3, 7.9 (note 2), 7.10 (note 2)
  • note 1 -- assume the machine has a branch delay slot that needs to be filled (ie, assume the original code has a nop after the branch). So you need to assume a pipeline similar to 6.36, but with a branch delay slot. In such an architecture, then, we would still need to squash two instructions after the BDS instruction on a taken branch.
  • P7 -- Assume the same code as P6, but running on a different pipeline. In this case, the machine has the following stages: IF ID X1 X2 M1 M2 WB. That is, ALU computation takes two cycles/stages, as does data memory access (the data needed for the alu or memory must be available at the beginning of X1 or M1, and the results are not available until the end of X2 or M2, respectively). Show forwarding and stalls for the code.
  • note 2 -- To be consistent with our discussions in class, multiply all addresses in the problem by 4 to get the byte addresses. Thus, addresses are 8, 12, 44, ... (this will not change the answers).
• Homework #7 -- Due November 30.
  • P&H 7.12, 7.15, 7.32, 7.35, 7.40 (note 1), P8, P9, W2
  • note 1 -- assume a 512 KB direct-mapped cache with 32-byte cache blocks.
  • P8 -- Program P running on Processor C achieves an instruction cache miss rate of 6% and a data cache miss rate of 9%. Assume a miss penalty of 25 cycles, that 20% of all instructions are loads, and that we never stall for stores. If the base CPI (ignoring the effect of cache misses) is 1.3, what is the total CPI?
  • P9 -- The equation for MCPI in class assumed a single level memory hierarchy. Derive the MCPI equation for a 2-level cache configuration with separate data and instruction L1 caches, backed up by a unified L2 cache. Use the terms L1DMR, L1IMR, L2MR, L1MP, L2MP, etc.
  • W2 -- Using the web, find the on-chip cache configuration (as much detail as you can find) for the following processors: Intel Pentium 4 E, Intel Pentium Processor Extreme Edition, AMD Opteron 850.

Note, the homework may include some problems on the CD and not in the book, and even include some problems ("For More Practice" from the CD) for which they make the solutions readily available. For those ("for more practice") problems only, you may consult the answers, but please do so only after solving them (then you can go back and correct).

Very approximate Reading and Exam Schedule:
 

Date	Topic	Critical	Important	Informative
Sept 21	Introduction	1.2	-	1.1, 1.3, 1.4
Sept 26	ISA	2.1-2.6,2.9	2.13,2.15,2.16	2.7,2.8,2.10-2.12
Sept 28	ISA	-	-	-
Oct 3	Performance	4.1-4.3,4.5	4.4	-
Oct 5	Computer Arithmetic	3.1-3.4,B.5		B.6
Oct 10		3.5-3.6	3.8	3.7
Oct 12	Single-Cycle CPU	5.1,5.3,5.4	5.2
Oct 17	Single-Cycle CPU Control, Multi-cycle CPU	5.5		C.3
Oct 19	Microprogramming and Exceptions	5.6		5.7
Oct 24	Pipelining	6.1,6.2
Oct 26	Data Hazards	6.4,6.5
Oct 31	Midterm (subject to confirmation)
Nov 2
Nov 7	Control Hazards	6.6		6.8
Nov 9	Advanced Pipelining	6.9, 6.10
Nov 14	Cache Basics	7.1-7.2
Nov 16
Nov 21	Better Caches	7.3, 7.5	7.6
Nov 23	Thanksgiving
Nov 28
Nov 30
Dec 5	Final, 3:00